Wright etch

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Margaret Wright Jenkins; 1936-2018 Margaret Wright Jenkins 2014.jpg
Margaret Wright Jenkins; 1936–2018

The Wright etch (also Wright-Jenkins etch) is a preferential etch for revealing defects in <100>- and <111>-oriented, p- and n-type silicon wafers used for making transistors, microprocessors, memories, and other components. Revealing, identifying, and remedying such defects is essential for progress along the path predicted by Moore's law. It was developed by Margaret Wright Jenkins (1936-2018) in 1976 while working in research and development at Motorola Inc. in Phoenix, AZ. It was published in 1977. [1] This etchant reveals clearly defined oxidation-induced stacking faults, dislocations, swirls and striations with minimum surface roughness or extraneous pitting. These defects are known causes of shorts and current leakage in finished semiconductor devices (such as transistors) should they fall across isolated junctions. A relatively low etch rate (~1 micrometre per minute) at room temperature provides etch control. The long shelf life of this etchant allows the solution to be stored in large quantities. [1]

Contents

Etch formula

The composition of the Wright etch is as follows:

In mixing the solution, the best results are obtained by first dissolving the copper nitrate in the given amount of water; otherwise the order of mixing is not critical.

Etch mechanism

The Wright etch consistently produces well-defined etch figures of common defects on silicon surfaces. This attribute is attributed to the interactions of the selected chemicals in the formula. Robbins and Schwartz [2] [3] [4] described chemical etching of silicon in detail using an HF, HNO3 and H2O system; and an HF, HNO3, H2O and CH3COOH (acetic acid) system. Briefly, the etching of silicon is a two-step process. First, the top surface of the silicon is converted into a soluble oxide by a suitable oxidizing agent(s). Then the resulting oxide layer is removed from the surface by dissolution in a suitable solvent, usually HF. This is a continuous process during the etch cycle. In order to delineate a crystal defect, the defect area must be oxidized at a slower or faster rate than the surrounding area thereby forming a mound or pit during the preferential etch process.

In the present system, the silicon is oxidized with HNO3, CrO3 solution (which in this case contains the Cr2O72− dichromate ion, since the pH is low - see the phase diagram in chromic acid) and Cu (NO3)2. The dichromate ion, a strong oxidizing agent, is considered to be the principal oxidizing agent. The ratio of HNO3 to CrO3 solution stated in the formula produces a superior etched surface. Other ratios produce less desirable finishes. With the addition of a small amount of Cu (NO3)2, the definition of the defect was enhanced. Therefore, it is believed that the Cu (NO3)2 affects the localized differential oxidation rate at the defect site. The addition of the acetic acid gave the background surface of the etched silicon a smooth finish. It is theorized that this effect is attributed to the wetting action of the acetic acid which prevents the formation of bubbles during etching.

All experimental preferential etching to show defects was done on cleaned and oxidized wafers. All oxidations were performed at 1200 °C in steam for 75 minutes. Figure 1 (a) shows oxidation-induced stacking faults in <100>-oriented wafers after 30 minutes Wright etch, (b) and (c) show dislocation pits on <100>- and <111>-oriented wafers respectively after 20 minutes Wright etch. [1]

Figure 1 (a),(b),(c) Fig1a.b.c.jpg
Figure 1 (a),(b),(c)

Figure 1 (a) shows oxidation-induced stacking faults on a <100>-oriented, 7-10 Ω-cm, boron-doped wafer after 30 minutes Wright etch (the A arrow in this figure points to the shape of faults that intersect the surface, while B points to bulk faults). Figure 1 (b) and (c) show dislocation pits on <100>- and <111>-oriented wafers respectively after 20 minutes Wright etch. [1]

Summary

This etch process is a quick and reliable method of determining the integrity of pre-processed polished silicon wafers or to reveal defects that may be induced at any point during wafer processing. It has been demonstrated that Wright etch is superior in revealing stacking faults and dislocation etch figures when compared with those revealed by Sirtl [5] and Secco etchings. [6]

This etch is widely used in failure analysis of electrical devices at various wafer processing stages. [7] [8] In comparison, the Wright etch was often the preferred etchant to reveal defects in silicon crystals. [7] [8]

Figure 2 (a),(b),(c): Wright etch comparison micrographs Wright.Etch.Fig2a.b.c.jpg
Figure 2 (a),(b),(c): Wright etch comparison micrographs

Figure 2 shows a comparison of oxidation-induced stacking fault delineation on <100>-oriented wafers after Wright etch, Secco and Sirtl etch respectively. [1]

Figure 3 shows a comparison of dislocation pits delineation on <100>-oriented wafers after Wright etch, Secco and Sirtl etch. The final figure 4 shows a comparison of dislocation pits revealed on a <111>-oriented wafer after etching with Wright etch, Secco and Sirtl etch respectively. [1]

Figure 3 (a),(b),(c): Wright etch comparison micrographs Wright.Etch.Fig3a.b.c.jpg
Figure 3 (a),(b),(c): Wright etch comparison micrographs

Figure 3 shows a comparison of dislocation delineation on a <100>-oriented, 10-20 Ω-cm, boron doped wafer after oxidation and preferential etching. (a) After 20 minutes Wright etch, (b) 10 minutes Secco etch and (c) 6 minutes Sirtl etch. [1]

Figure 4 (a),(b),(c): Wright etch comparison micrographs Wright.Etch.Fig4a.b.c.jpg
Figure 4 (a),(b),(c): Wright etch comparison micrographs

Figure 4 shows a comparison of dislocation delineation on a <111>-oriented, 10-20 Ω-cm, boron-doped wafer after oxidation and preferential etching. (a) After 10 minutes Wright etch, (b) 10 minutes Secco etch and (c) 3 minutes Sirtl etch. The arrows indicate slip direction. [1]

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References

  1. 1 2 3 4 5 6 7 8 9 10 11 12 Wright Jenkins, Margaret (May 1977) [1976-08-27, 1976-12-16]. "A New Preferential Etch for Defects in Silicon Crystals". Journal of the Electrochemical Society . Motorola Incorporated, Motorola Semiconductor Products Group, Phoenix, Arizona, USA: The Electrochemical Society (ECS). 124 (5): 757–759. doi:10.1149/1.2133401 . Retrieved 2019-04-06.
  2. ↑ Robbins, Harry; Schwartz, Bertram (June 1959) [1958-04-30]. "Chemical Etching of Silicon: Part I. The System HF, HNO3, H2O, and HC2H3O2". Journal of the Electrochemical Society . The Electrochemical Society (ECS). 106 (6): 505–508. doi:10.1149/1.2427397.
  3. ↑ Robbins, Harry; Schwartz, Bertram (February 1960) [1959-04-06]. "Chemical Etching of Silicon: Part II. The System HF, HNO3, H2O, and HC2H3O2". Journal of the Electrochemical Society . The Electrochemical Society (ECS). 107 (2): 108–111. doi:10.1149/1.2427617.
  4. ↑ Robbins, Harry; Schwartz, Bertram (August 1961) [1960-08-08, 1960-12-28]. "Chemical Etching of Silicon: Part III. A Temperature Study in the Acid System". Journal of the Electrochemical Society . The Electrochemical Society (ECS). 108 (4): 365–372. doi:10.1149/1.2428090.
  5. ↑ Sirtl, Erhard; Adler, Annemarie (August 1961). "Chromsäure-Flussäure als Spezifisches System zur Ätzgrubenentwicklung auf Silizium". Zeitschrift für Metallkunde (ZfM) (in German). 52 (8): 529–534. NAID   10011334657.
  6. ↑ Secco d'Aragona, F. (July 1972) [1971-12-20, 1972-03-03]. "Dislocation Etch for (100) Planes in Silicon". Journal of the Electrochemical Society . The Electrochemical Society (ECS). 119 (7): 948–951. doi:10.1149/1.2404374.
  7. 1 2 Su, Garth K.; Jin, Da; Kim, Sung-Rae; Chan, Tze-Ho; Balan, Hari; Lin, Yung-Tao; Han, Kyung-Joon; Hsia, Steve (December 2003). "CMOS: Defect Avoidance - Pipeline Defects in Flash Devices Associated with Rings OSF" (PDF). Semiconductor Manufacturing: 144–151. Archived from the original (PDF) on 2016-03-03. Retrieved 2019-04-06.
  8. 1 2 "Chapter 6". Defect Etching in Silicon. 2002. Archived from the original on 2019-04-06. Retrieved 2019-04-06.
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